Etch stop layer removal for capacitance reduction in damascene top via integration

ABSTRACT

A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.

BACKGROUND

The present invention generally relates to fabrication methods andresulting structures for integrated circuits (ICs), and morespecifically, to fabrication methods and resulting interconnectstructures of ICs.

The use of very large scale integration (VLSI) or ultra large scaleintegration (VLSI) in the fabrication of ICs requires the manufacture ofsophisticated interconnect structures including conductive wiringinterconnect networks that connect individual devices in a semiconductorchip to one another. Typically, the wiring interconnect networks includetwo types of interconnect elements (often simply referred to asinterconnects) that serve as electrical conductors, namely, conductiveline features (also referred to as “conductive lines”) that traverse adistance across the chip, and conductive via features (also referred toas “conductive vias”) that connect the conductive lines at differentlevels. The conductive lines and conductive vias are made of conductivematerial, such as aluminum or copper, and are electrically insulated byinterlayer dielectrics (ILD).

SUMMARY

Embodiments of the invention are directed to a method for forming aninterconnect structure. The method includes forming at least onesecond-level interconnect in a sacrificial dielectric layer that isformed on an upper surface of a sacrificial etch stop layer, andremoving the sacrificial dielectric layer and the sacrificial etch stoplayer while maintaining the at least one second-level interconnect so asto expose an underlying dielectric layer. The method further includesdepositing a replacement dielectric layer on an upper surface of theunderlying dielectric layer to embed the at least one second-levelinterconnect in the replacement dielectric layer

Embodiments of the invention are directed to a method for forming awiring interconnect network included in an interconnect structure. Anon-limiting example of the method includes forming a sacrificial etchstop layer on an upper surface of a dielectric layer to cover at leastone first-level interconnect embedded in the dielectric layer, andforming a sacrificial dielectric layer on an upper surface of thesacrificial etch stop layer. The method further includes forming atleast one second-level interconnect that extends through the sacrificialdielectric layer and sacrificial etch stop layer to contact the at leastone first-level interconnect, and removing the sacrificial dielectriclayer and sacrificial etch stop layer while preserving the at least onesecond-level interconnect. The method further includes depositing areplacement dielectric layer on an upper surface of the dielectric layerto cover the at least one first-level interconnect and embed the atleast one second-level interconnect in the replacement dielectric layer.

Embodiments of the invention are directed to an interconnect structure.The interconnect structure includes one or more first-level interconnectin a dielectric layer and one or more second-level interconnects in areplacement dielectric layer stacked on the dielectric layer. Thereplacement dielectric layer directly contacts the dielectric layer.

Additional technical features and benefits are realized through thetechniques of the present invention. Embodiments and aspects of theinvention are described in detail herein and are considered a part ofthe claimed subject matter. For a better understanding, refer to thedetailed description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The specifics of the exclusive rights described herein are particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features and advantages ofthe embodiments of the invention are apparent from the followingdetailed description taken in conjunction with the accompanying drawingsin which:

FIG. 1 depicts a cross-sectional view of an intermediate interconnectstructure including first-level interconnects formed in a dielectriclayer according to one or more embodiments of the invention;

FIG. 2 depicts a cross-sectional view of the interconnect structureafter forming a sacrificial etch stop layer that covers the first-levelinterconnects according to one or more embodiments of the invention;

FIG. 3 depicts a cross-sectional view of the interconnect structurefollowing deposition of a sacrificial dielectric layer on an uppersurface of the sacrificial etch stop layer according to one or moreembodiments of the invention;

FIG. 4 depicts a cross-sectional view of the interconnect structureafter forming a trench in the sacrificial dielectric layer according toone or more embodiments of the invention;

FIG. 5 depicts a cross-sectional view of the interconnect structureafter filling the trench with a conductive material to form asecond-level interconnect according to one or more embodiments of theinvention;

FIG. 6 depicts a cross-sectional view of the interconnect structureafter removing the sacrificial dielectric layer according to one or moreembodiments of the invention;

FIG. 7 depicts a cross-sectional view of the interconnect structureafter removing the sacrificial etch stop layer to expose the underlyingfirst-level interconnects according to one or more embodiments of theinvention; and

FIG. 8 depicts a cross-sectional view of a completed interconnectstructure following deposition of a replacement dielectric layer thatcovers the second-level interconnect and first-level interconnectsaccording to one or more embodiments of the invention.

The diagrams depicted herein are illustrative. There can be manyvariations to the diagrams or the operations described therein withoutdeparting from the spirit of the invention. For instance, the actionscan be performed in a differing order or actions can be added, deletedor modified.

In the accompanying figures and following detailed description of thedescribed embodiments of the invention, the various elements illustratedin the figures are provided with two or three-digit reference numbers.With minor exceptions, the leftmost digit(s) of each reference numbercorrespond to the figure in which its element is first illustrated.

DETAILED DESCRIPTION

It is understood in advance that although example embodiments of theinvention are described in connection with a particular interconnectarchitecture, embodiments of the invention are not limited to theparticular interconnect architectures or materials described in thisspecification. Rather, embodiments of the present invention are capableof being implemented in conjunction with any other type of interconnectarchitecture or materials now known or later developed.

For the sake of brevity, conventional techniques related tosemiconductor device and integrated circuit (IC) fabrication may or maynot be described in detail herein. Moreover, the various tasks andprocess steps described herein can be incorporated into a morecomprehensive procedure or process having additional steps orfunctionality not described in detail herein. In particular, varioussteps in the manufacture of semiconductor devices andsemiconductor-based ICs are well known and so, in the interest ofbrevity, many conventional steps will only be mentioned briefly hereinor will be omitted entirely without providing the well-known processdetails.

Turning now to an overview of technologies that are more specificallyrelevant to aspects of the present invention, ICs are fabricated in aseries of stages, including a front-end-of-line (FEOL) stage, amiddle-of-line (MOL) stage, and a back-end-of-line (BEOL) stage. Theprocess flows for fabricating modern ICs are often identified based onwhether the process flows fall in the FEOL stage, the MOL stage, or theBEOL stage. Generally, the FEOL stage is where device elements (e.g.,transistors, capacitors, resistors, etc.) are patterned in thesemiconductor substrate/wafer. The FEOL stage processes include waferpreparation, isolation, gate patterning, and the formation of wells,source/drain (S/D) regions, extension junctions, silicide regions, andliners. The MOL stage typically includes process flows for forming thecontacts (e.g., CA) and other structures that communicatively couple toactive regions (e.g., gate, source, and drain) of the device element.For example, the silicidation of source/drain regions, as well as thedeposition of metal contacts, can occur during the MOL stage to connectthe elements patterned during the FEOL stage.

Layers of interconnections (e.g., metallization layers) includeconductive lines that are formed above the logical and functional layersduring the BEOL stage to complete the IC. Most ICs need more than onemetallization, and as many as 5-12 layers can be formed in the BEOLprocess. The various BEOL layers and/or individual conductive lines areinterconnected by conductive vias. The combination of conductive linesand conductive vias form a wiring interconnect network that establishesall the necessary connections of the interconnect structure.

In multilayered interconnect structures described herein, “M” layers(e.g., M1 layer, M2 layer, etc.) denote metal line layers, while “V”layers denote conductive vias formed between adjacent M layers (e.g., V1is between the M1 and M2 layers). As used herein, a “top via” refers toa “Vx” layer via which is integrally formed from patterning the linebelow (an “Mx” layer) and which electrically couples the line below (an“Mx” layer) to a line above (an “Mx+1” layer).

Insulating dielectric materials are used throughout the layers of an ICto perform a variety of functions, including stabilizing the ICstructure and providing electrical isolation of the IC elements. Forexample, one or more conductive lines in the BEOL region of the IC areisolated by dielectric layers to prevent the conductive lines fromcreating a short circuit. One or more conductive vias are typicallyformed in the dielectric layers to establish a connection between aconductive line formed at a first layer and another conductive lineformed at a second layer.

The continued scaling of semiconductor devices has resulted inchallenging fabrication requirements, especially when fabricating eversmaller metallization layers. To increase the number of circuits thatcan be provided on a chip, the semiconductor industry has repeatedlyshrunk the transistor gate length and the chip size. As a consequence,the interconnect structure that forms the metallic circuitry has alsoshrunk. As the integrated circuit (IC) footprint continues to decrease,structural elements (lines, vias, etc.) and spacing tolerances (i.e.,feature to feature spacing) also decrease, complicating themanufacturing process.

Fabricating intricate elements (e.g., conductive lines and vias) ofinterconnect structures within increasingly smaller wafer footprints isone of the most process-intensive and cost-sensitive portions ofsemiconductor IC fabrication. Advanced BEOL processes incorporatephase-shifting, optical proximity correction, and other practices tosatisfy these scaling demands, and can achieve a line to line pitchbelow 30 nm. There are challenges, however, in fabricating advancedinterconnects having a line to line pitch below 30 nm. For example,high-k etch stop layers are typically interposed between a given pair ofdielectric layers to properly etch the conductive vias. However,reducing the footprint of the interconnect structures increases anundesirable capacitance effect resulting from electrical interactionsbetween the metal lines, the high-k etch stop layer, and the dielectriclayers.

In addition, conventional fabrication processes used to form aninterconnect structure typically deposit a second dielectric layer onthe underlying dielectric layer, and then perform via/line trench andfill operations to form a conductive via and/or line in the seconddielectric layer. The trench and fill operations, however, cause defects(e.g., cracks and weakened portions) in the second dielectric layer.These defects undesirably increase the dielectric constant of the seconddielectric layer. As a result, the actual dielectric constant of thedielectric layer can vary or deviate from the intended or targeteddielectric constant.

Turning now to an overview of aspects of the present invention, one ormore embodiments of the invention address the above-described challengesof the prior art by providing a new interconnect structure and a methodfabricating the same, which excludes the conventional high-k etch stoplayer between a stack of dielectric layers or metallization layers. Inthis manner, the undesirable capacitance effect produced by conventionalinterconnect devices can be significantly reduced or even eliminatedaltogether.

In addition, the interconnect structure according to embodiments of theinvention described herein includes a replacement dielectric layer thatembeds a conductive via therein. Because the replacement dielectriclayer is deposited after formation of the conductive via, thereplacement dielectric layer is not susceptible to damage caused by theconventional via/line formation processes. In this manner, a targeteddielectric constant value of the replacement dielectric layer can bemaintained.

Turning now to a more detailed description of aspects of the presentinvention, FIG. 1 depicts a cross-sectional view of an intermediateinterconnect structure 100 following one or more processing operationsaccording to one or more embodiments of the invention. In the presentspecification and claims, an “intermediate” interconnect structure isdefined as an interconnect structure in a stage of fabrication prior toa final stage.

Known fabrication operations have been used to form the interconnectstructure 100 such that it includes one or more first-levelinterconnects 102 in a dielectric layer 104. The first-levelinterconnects 102 can include, but are not limited to, conductive linesand conductive vias. Although the first-level interconnects aredescribed as conductive lines 102 going forward, it should beappreciated that one or more conductive vias can be formed in thedielectric layer 104. Further, while only two conductive lines 102 areshown, it should be appreciated that less or more conductive lines 102can be included in the dielectric layer 104 without departing from thescope of the invention. The conductive lines 102 includes a conductivematerial formed or deposited in a trench in the dielectric layer 104using known back-end-of-line (BEOL) processes. In some embodiments ofthe invention, the conductive lines 102 are overfilled above a surfaceof the trench (not shown), forming overburdens that can be removedusing, for example, a chemical-mechanical planarization (CMP) process.

The conductive lines 102 can be made of any suitable conductingmaterial, such as, for example, metal (e.g., tungsten, titanium,tantalum, ruthenium, zirconium, cobalt, copper, aluminum, platinum),alloys thereof (such as AlCu, CuMn, CuTi, or the like), conductingmetallic compound material (e.g., tantalum nitride, titanium nitride,tantalum carbide, titanium carbide, titanium aluminum carbide, tungstensilicide, tungsten nitride, cobalt silicide, nickel silicide),conductive carbon, or any suitable combination of these materials. Insome embodiments of the invention, the conductive lines 102 are copperlines (copper interconnects). The conductive lines 102 can be formed ordeposited using, for example, CVD, PECVD, PVD, sputtering, plating,chemical solution deposition, and electroless plating. In one or moreembodiments of the invention, the conductive lines have a widthextending parallel with the upper surface of the dielectric layer 104ranging from about 5 nm to about 20 nm and a height extending orthogonalwith respect to the width ranging from about 10 nm to about 50 nm

The dielectric layer 104 (sometimes referred to as an interlayerdielectric) serves as an isolation structure for electrically conductiveelements formed therein (e.g., conductive lines, via, etc.). Thedielectric layer 104 can be made of any suitable dielectric material,such as, for example, low-k dielectrics (materials having a smalldielectric constant relative to silicon dioxide, i.e., less than about3.9), porous silicates, carbon doped oxides, silicon dioxides, siliconnitrides, silicon oxynitrides, silicon carbide (SiC), or otherdielectric materials. Any known manner of forming the dielectric layer104 can be utilized, such as, for example, CVD, PECVD, ALD, flowableCVD, spin-on dielectrics, or PVD.

Turning to FIG. 2, the interconnect structure 100 is illustrated afterforming a sacrificial etch stop layer 106 that covers the conductivelines 102 according to one or more embodiments of the invention. Thesacrificial etch stop layer 106 can be made of, for example, a high-kmaterial. As used herein, high-k materials are those having a largedielectric constant relative to silicon dioxide, i.e., more than about3.9, and preferably more than about 7.0. In one or more non-limitingembodiments of the invention, the sacrificial etch stop layer 106 isformed directly on an upper surface of the dielectric layer 104 using,for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD.

Examples of high-k materials include but are not limited to metal oxidessuch as hafnium oxide, hafnium silicon oxide, hafnium siliconoxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide,zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide,titanium oxide, barium strontium titanium oxide, barium titanium oxide,strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandiumtantalum oxide, and lead zinc niobate. The high-k materials can furtherinclude dopants such as lanthanum and aluminum. In some embodiments ofthe invention, the sacrificial etch stop layer 106 can be formed ordeposited to a thickness of about 0.5 nm to about 25 nm, for example 10nm, although other thicknesses are within the contemplated scope of theinvention. By forming the sacrificial etch stop layer 106 from a high-kmaterial, a selective etching process can be performed that allows thesacrificial etch stop layer 106 to be subsequently etched away andremoved while preserving one or more remaining elements of theinterconnect structure 100.

Referring to FIG. 3, the interconnect structure 100 is illustratedfollowing deposition of a sacrificial dielectric layer 108 on an uppersurface of the sacrificial etch stop layer 106 according to one or moreembodiments of the invention. The sacrificial dielectric layer 108 canbe made of a low-k dielectric material (e.g., materials having a smalldielectric constant relative to silicon dioxide, i.e., less than about3.9), porous silicates, carbon doped oxides, silicon dioxides, siliconnitrides, silicon oxynitrides, silicon carbide (SiC), or otherdielectric materials. Any known manner of forming the sacrificialdielectric layer 108 can be utilized, such as, for example, CVD, PECVD,ALD, flowable CVD, spin-on dielectrics, or PVD. By forming thesacrificial dielectric layer 108 from a low-k material, a selectiveetching process can be performed that allows the sacrificial dielectriclayer 108 to be subsequently etched away and removed while preservingthe underlying sacrificial etch stop layer 106.

Turning now to FIG. 4, the interconnect structure 100 is illustratedafter forming a trench 110 in the sacrificial dielectric layer 108according to one or more embodiments of the invention. In someembodiments of the invention, portions of the sacrificial dielectriclayer 108 and portions of the sacrificial etch stop layer 106 areremoved (patterned) to form the trench 110, which exposes a surface ofone or more conductive lines 102. In one or more embodiments of theinvention, the trench 110 has a width extending parallel with the uppersurface of the sacrificial dielectric layer 108 ranging from about 5 nmto about 20 nm and a height extending orthogonal with respect to thewidth ranging from about 10 nm to about 50 nm

The sacrificial dielectric layer 108 and the sacrificial etch stop layer106 can be patterned using a wet etch, a dry etch, or a combination ofsequential wet and/or dry etches. In some embodiments of the invention,the sacrificial dielectric layer 108 is removed selective to thesacrificial etch stop layer 106 and the exposed portion of thesacrificial etch stop layer 106 is removed to expose the surface of anunderlying conductive line 102. In one or more non-limiting embodimentsof the invention, an etching processes including fluorine-containingchemistries can etch low-k materials such as, for example, SiO₂,selective to etch stop materials such as, for example, AlN.

Referring to FIG. 5, the interconnect structure 100 is illustrated afterfilling the trench 110 with a conductive material according to one ormore embodiments of the invention. Accordingly, a second-levelinterconnect 112 is formed at a second level of the interconnectstructure 100. The second-level interconnect 112 can include, but is notlimited to, a conductive via and/or a conductive line. Although thesecond-level interconnect is described as conductive via 112 goingforward, it should be appreciated that one or more conductive lines canbe formed in the second-level of the interconnect structure. Further,while only one conductive via 112 is shown, it should be appreciatedthat more conductive vias 112 can be formed without departing from thescope of the invention.

In one or more non-limiting embodiments of the invention, the conductivevia 112 can be formed by filling the trench 110 with a conductivematerial. Accordingly, the conductive via 112 can be formed such that itdirectly contacts one or more underlying conductive lines 102. Althougha conductive via 112 is described above, it should be appreciated thatsimilar processes can be used to form a conductive line in thesacrificial dielectric layer 108.

In one or more non-limiting embodiments of the invention, the metalmaterial of the conductive via includes, but is not limited to, copperor a non-copper metal (e.g., tungsten, titanium, tantalum, ruthenium,zirconium, cobalt, aluminum, platinum), alloys thereof, conductingmetallic compound material (e.g., tantalum nitride, titanium nitride,tantalum carbide, titanium carbide, titanium aluminum carbide, tungstensilicide, tungsten nitride, cobalt silicide, nickel silicide),conductive carbon, or any suitable combination of these materials. Insome embodiments of the invention, the conductive via 112 is formed froma same material as the conductive line 102. For example, the conductivevia 112 and the conductive line 102 can be made cobalt or ruthenium. Insome embodiments of the invention, the conductive via 112 and theconductive line 102 are made of different conductive materials. Forexample, the conductive via 112 can be made cobalt or ruthenium and theconductive line 102 can be made of copper. In some embodiments of theinvention, the trench 110 is overfilled above a surface of thesacrificial dielectric layer 108, forming overburdens that can beremoved using, for example, a CMP process.

Accordingly, the upper surface of the conductive via 112 can be formedflush (i.e., co-planar) with respect to the upper surface of thesacrificial dielectric layer 108.

Turning now to FIG. 6, the interconnect structure 100 is illustratedafter removing the sacrificial dielectric layer 108 (see FIG. 5)according to one or more embodiments of the invention. In one or morenon-limiting embodiments of the invention, the sacrificial dielectriclayer 108 is removed using a wet etch, a dry etch, or a combination ofsequential wet and/or dry etches. In some embodiments of the invention,the sacrificial dielectric layer 108 is removed selective to theconductive via 112 and the selective etch stop layer 106. In one or morenon-limiting embodiments of the invention, an etching process includingfluorine (F)-containing chemistries can etch dielectrics such as low-kdielectrics, for example, selective to high-k materials and metalmaterials. Accordingly, the upper surface of the sacrificial etch stoplayer 106 is exposed, along with a portion of the sidewalls and uppersurface of the conductive via 112.

Referring to FIG. 7, the interconnect structure 100 is illustrated afterremoving the sacrificial etch stop layer 106 (see FIG. 6) according to anon-limiting embodiment of the invention. In one or more non-limitingembodiments of the invention, the sacrificial etch stop layer 106 isremoved selective to the conductive via 112, the underlying dielectriclayer 104, and the conductive lines 102. In one or more non-limitingembodiments of the invention, an etching process including a modifiedfluorine (F)-containing chemistry can etch the sacrificial etch stoplayer 106 selective to the conductive via 112. Accordingly, thesidewalls and upper surface of the conductive via 112 are completelyexposed, along with surfaces of the conductive lines 102 and thedielectric layer 104.

Turning now to FIG. 8, the interconnect structure 100 is illustratedfollowing deposition of a replacement dielectric layer 114 according toa non-limiting embodiment of the invention. In one or more non-limitingembodiments of the invention, the replacement dielectric layer 114 isdeposited directly on the upper surface of the dielectric layer 104 tocover the conductive lines 102 and embed the conductive via 112 therein.The replacement dielectric layer 114 can be deposited using, forexample, CVD, PECVD, ALD, flowable CVD, spin-on dielectrics, or PVD, andcan be formed having any suitable thickness or height. In someembodiments of the invention, the replacement dielectric layer 114 isdeposited to a height of about 50 nm above the surface of the underlyingdielectric layer 104, although other heights are within the contemplatedscope of the invention. In one or more non-limiting embodiments of theinvention, the replacement dielectric layer 114 can be deposited at aheight that extends above the conductive via 112. A CMP process can thenbe performed that stops on an upper surface of the conductive via 112.Accordingly, the upper surface of the conductive via 112 can be formedflush (i.e., co-planar) with respect to the upper surface of thereplacement dielectric layer 114.

The replacement dielectric layer 114 can be made of various dielectricmaterials, such as, for example, low-k dielectrics, ultra-low-kdielectrics, porous silicates, carbon doped oxides, silicon dioxides,silicon nitrides, silicon oxynitrides, silicon carbide (SiC), or otherdielectric materials. In some embodiments of the invention, thereplacement dielectric layer 114 is the same material as the underlyingdielectric layer 104, forming a continuous dielectric region.

As discussed previously herein, conventional techniques of forming aconductive line or via in a dielectric layer can cause defects (e.g.,cracks, weakened portions, etc.) in the dielectric layer, which canundesirably increase the dielectric constant of the dielectric layerbeyond a targeted dielectric constant value. Advantageously, thereplacement dielectric layer 114 serves to replace the sacrificialdielectric layer 108. The replacement dielectric layer 114, however,excludes etch-induced damages or defects adjacent to (e.g., extendingfrom or contacting the conductive via 112). That is, because thereplacement dielectric layer 114 is formed after the conductive via 112,no etch-induced damages or defects are formed in the vicinity of theconductive via 112 while also allowing for the replacement dielectriclayer 114 to achieve a targeted dielectric constant. In some embodimentsof the invention, maintaining the targeted dielectric layer allows forforming the underlying dielectric layer 104 with a first dielectricconstant value (e.g., that is less than 3.9), while forming thereplacement dielectric layer 114 with a second dielectric constant value(e.g., that is less than 3.9). In other embodiments of the invention,maintaining the targeted dielectric layer allows for forming acontinuous dielectric region (defined by the underlying dielectric layer104 and the replacement dielectric layer 114) having a non-varyingdielectric constant value. In some embodiments, the continuousdielectric region defined by the underlying dielectric layer 104 and thereplacement dielectric layer 114 is formed of the same dielectricmaterial. However, the dielectric constant value of the continuousdielectric region does not vary with respect to the underlyingdielectric layer 104 because the replacement dielectric layer 114 isformed after the conductive via 112 such that no etch-induced damages ordefects are formed therein.

As described herein, various non-limiting embodiments of the inventionprovide a new multilevel interconnect structure that includes a wiringinterconnect network, while completely excluding an etch stop layerbetween a first dielectric layer at a first level and a seconddielectric layer located at an immediate lower level or upper level. Inthis manner, the undesirable capacitance effect produced by conventionalinterconnect devices can be significantly reduced or even eliminatedaltogether.

In addition, the interconnect structure according to embodiments of theinvention described herein includes a replacement dielectric layer thatembeds a conductive via therein. Because the replacement dielectriclayer is deposited after formation of the conductive via, thereplacement dielectric layer is not susceptible to damage caused by theconventional via/line formation processes. In this manner, a targeteddielectric constant value of the replacement dielectric layer can bemaintained

The methods and resulting structures described herein can be used in thefabrication of IC chips. The resulting IC chips can be distributed bythe fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includes ICchips, ranging from toys and other low-end applications to advancedcomputer products having a display, a keyboard or other input device,and a central processor.

Various embodiments of the present invention are described herein withreference to the related drawings. Alternative embodiments can bedevised without departing from the scope of this invention. Althoughvarious connections and positional relationships (e.g., over, below,adjacent, etc.) are set forth between elements in the followingdescription and in the drawings, persons skilled in the art willrecognize that many of the positional relationships described herein areorientation-independent when the described functionality is maintainedeven though the orientation is changed. These connections and/orpositional relationships, unless specified otherwise, can be direct orindirect, and the present invention is not intended to be limiting inthis respect. Similarly, the term “coupled” and variations thereofdescribes having a communications path between two elements and does notimply a direct connection between the elements with no interveningelements/connections between them. All of these variations areconsidered a part of the specification. Accordingly, a coupling ofentities can refer to either a direct or an indirect coupling, and apositional relationship between entities can be a direct or indirectpositional relationship. As an example of an indirect positionalrelationship, references in the present description to forming layer “A”over layer “B” include situations in which one or more intermediatelayers (e.g., layer “C”) is between layer “A” and layer “B” as long asthe relevant characteristics and functionalities of layer “A” and layer“B” are not substantially changed by the intermediate layer(s).

The following definitions and abbreviations are to be used for theinterpretation of the claims and the specification. As used herein, theterms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” “contains” or “containing,” or any other variation thereof,are intended to cover a non-exclusive inclusion. For example, acomposition, a mixture, process, method, article, or apparatus thatcomprises a list of elements is not necessarily limited to only thoseelements but can include other elements not expressly listed or inherentto such composition, mixture, process, method, article, or apparatus.

Additionally, the term “exemplary” is used herein to mean “serving as anexample, instance or illustration.” Any embodiment or design describedherein as “exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs. The terms “at least one”and “one or more” are understood to include any integer number greaterthan or equal to one, i.e. one, two, three, four, etc. The terms “aplurality” are understood to include any integer number greater than orequal to two, i.e. two, three, four, five, etc. The term “connection”can include an indirect “connection” and a direct “connection.”

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedcan include a particular feature, structure, or characteristic, butevery embodiment may or may not include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

For purposes of the description hereinafter, the terms “upper,” “lower,”“right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” andderivatives thereof shall relate to the described structures andmethods, as oriented in the drawing figures. The terms “overlying,”“atop,” “on top,” “positioned on” or “positioned atop” mean that a firstelement, such as a first structure, is present on a second element, suchas a second structure, wherein intervening elements such as an interfacestructure can be present between the first element and the secondelement. The term “direct contact” means that a first element, such as afirst structure, and a second element, such as a second structure, areconnected without any intermediary conducting, insulating orsemiconductor layers at the interface of the two elements.

Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,”“upper,” and the like, are used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device can be otherwise oriented (e.g., rotated 90degrees or at other orientations), and the spatially relativedescriptors used herein should be interpreted accordingly.

The terms “about,” “substantially,” “approximately,” and variationsthereof, are intended to include the degree of error associated withmeasurement of the particular quantity based upon the equipmentavailable at the time of filing the application. For example, “about”can include a range of ±8% or 5%, or 2% of a given value.

The phrase “selective to,” such as, for example, “a first elementselective to a second element,” can refer to an etching process capableof etching a first element while preserving a second element or withoutsubstantially etching the second element. In other instances, the phrase“selective to” means that the first element can be etched and the secondelement can act as an etch stop.

The term “conformal” (e.g., a conformal layer or a conformal deposition)means that the thickness of the layer is substantially the same on allsurfaces, or that the thickness variation is less than 15% of thenominal thickness of the layer.

The terms “epitaxial growth and/or deposition” and “epitaxially formedand/or grown” mean the growth of a semiconductor material (crystallinematerial) on a deposition surface of another semiconductor material(crystalline material), in which the semiconductor material being grown(crystalline overlayer) has substantially the same crystallinecharacteristics as the semiconductor material of the deposition surface(seed material). In an epitaxial deposition process, the chemicalreactants provided by the source gases can be controlled and the systemparameters can be set so that the depositing atoms arrive at thedeposition surface of the semiconductor substrate with sufficient energyto move about on the surface such that the depositing atoms orientthemselves to the crystal arrangement of the atoms of the depositionsurface. An epitaxially grown semiconductor material can havesubstantially the same crystalline characteristics as the depositionsurface on which the epitaxially grown material is formed. For example,an epitaxially grown semiconductor material deposited on a {100}orientated crystalline surface can take on a {100} orientation. In someembodiments of the invention, epitaxial growth and/or depositionprocesses can be selective to forming on semiconductor surface, and mayor may not deposit material on exposed surfaces, such as silicon dioxideor silicon nitride surfaces.

As previously noted herein, for the sake of brevity, conventionaltechniques related to semiconductor device and integrated circuit (IC)fabrication may or may not be described in detail herein. By way ofbackground, however, a more general description of the semiconductordevice fabrication processes that can be utilized in implementing one ormore embodiments of the present invention will now be provided. Althoughspecific fabrication operations used in implementing one or moreembodiments of the present invention can be individually known, thedescribed combination of operations and/or resulting structures of thepresent invention are unique. Thus, the unique combination of theoperations described in connection with the fabrication of asemiconductor device according to the present invention utilize avariety of individually known physical and chemical processes performedon a semiconductor (e.g., silicon) substrate, some of which aredescribed in the immediately following paragraphs.

In general, the various processes used to form a micro-chip that will bepackaged into an IC fall into four general categories, namely, filmdeposition, removal/etching, semiconductor doping andpatterning/lithography. Deposition is any process that grows, coats, orotherwise transfers a material onto the wafer. Available technologiesinclude physical vapor deposition (PVD), chemical vapor deposition(CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE)and more recently, atomic layer deposition (ALD) among others.Removal/etching is any process that removes material from the wafer.Examples include etch processes (either wet or dry), chemical-mechanicalplanarization (CMP), and the like. Reactive ion etching (ME), forexample, is a type of dry etching that uses chemically reactive plasmato remove a material, such as a masked pattern of semiconductormaterial, by exposing the material to a bombardment of ions thatdislodge portions of the material from the exposed surface. The plasmais typically generated under low pressure (vacuum) by an electromagneticfield. Semiconductor doping is the modification of electrical propertiesby doping, for example, transistor sources and drains, generally bydiffusion and/or by ion implantation. These doping processes arefollowed by furnace annealing or by rapid thermal annealing (RTA).Annealing serves to activate the implanted dopants. Films of bothconductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators(e.g., various forms of silicon dioxide, silicon nitride, etc.) are usedto connect and isolate transistors and their components. Selectivedoping of various regions of the semiconductor substrate allows theconductivity of the substrate to be changed with the application ofvoltage. By creating structures of these various components, millions oftransistors can be built and wired together to form the complexcircuitry of a modern microelectronic device. Semiconductor lithographyis the formation of three-dimensional relief images or patterns on thesemiconductor substrate for subsequent transfer of the pattern to thesubstrate. In semiconductor lithography, the patterns are formed by alight sensitive polymer called a photo-resist. To build the complexstructures that make up a transistor and the many wires that connect themillions of transistors of a circuit, lithography and etch patterntransfer steps are repeated multiple times. Each pattern being printedon the wafer is aligned to the previously formed patterns and slowly theconductors, insulators and selectively doped regions are built up toform the final device.

The flowchart and block diagrams in the Figures illustrate possibleimplementations of fabrication and/or operation methods according tovarious embodiments of the present invention. Variousfunctions/operations of the method are represented in the flow diagramby blocks. In some alternative implementations, the functions noted inthe blocks can occur out of the order noted in the Figures. For example,two blocks shown in succession can, in fact, be executed substantiallyconcurrently, or the blocks can sometimes be executed in the reverseorder, depending upon the functionality involved.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments described. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdescribed herein.

What is claimed is:
 1. An interconnect structure comprising: at leastone first-level interconnect in a dielectric layer; and at least onesecond-level interconnect in a replacement dielectric layer stacked onthe dielectric layer, wherein the replacement dielectric layer directlycontacts the dielectric layer.
 2. The interconnect structure of claim 1,wherein the replacement dielectric layer excludes etch-induced damagesor defects adjacent to the conductive via.
 3. The interconnect structureof claim 2, wherein the at least one second-level interconnect directlycontacts the at least one first-level interconnect.
 4. The interconnectstructure of claim 3, wherein the interconnect structure completelyexcludes an etch stop layer between the dielectric layer and thereplacement dielectric layer.
 5. The interconnect structure of claim 2,wherein the dielectric layer has a first dielectric constant value thatis less than 3.9.
 6. The interconnect structure of claim 5, wherein thereplacement dielectric layer has a second dielectric constant value thatis less than the first dielectric constant.
 7. The interconnectstructure of claim 6, wherein the at least one first-level interconnectand the at least one second-level interconnect each comprise a metalmaterial.
 8. The interconnect structure of claim 2, wherein the at leastone first-level interconnect is a conductive line comprising a metalmaterial and the at least one second-level interconnect is a conductivevia comprising a metal material.